lunes, 5 de noviembre de 2012

The G1 and the Goettingen Family of Sequential Computers

by Wilhelm Hopmann  (qepd)

Nota: Yo nací el 13 de Marzo de 1950 - más o menos al mismo tiempo que mi padre comenzó el trabajo en “su” primera maquina. En años más tarde (Kinder, Primaria) ya fue usuario de la G1a para las tareas de aritmética.
Esta retrospectiva él redactó en Julio 1998, o sea 48 años despúes. 
Cornelio Hopmann

Wil-G1Mi padre haciendo las primeras pruebas de la G1 en Junio 1952, hace 60 años …

In the year 1947 a small party of computer scientists from the NPL at Teddington visited the British Occupation Zone of Germany in order to explore what had been done in that field of research in the last decade. Among others, J.P.Womersley, the Superintendent of the Mathematics Division of the NPL, Alan Turing and A. Porter were members of that party. On the German side, Alwin Walter from Darmstadt, Konrad Zuse and Heinz Billing and others were participants of a colloquium discussing the state of mathematics and of computing in Germany. It was only after that meeting, that Womersley told Billing about the NPL-plans for a computer much smaller than the famous ENIAC and using the bit-serial method of number processing. Afterwards Billing wrote about this privatissimum in his notebook and sketched the main working principle. Fig. 1 is the copy of a reproduction of that note. This is the very start of the development of computers at Goettingen.

In retrospect it might have been a stroke of luck, that Womersley didn't tell anything about the realization of the delay lines. Billing at first thought of using electrical delay lines, e.g. cables or chains of quadrupols, but eventually decided on the use of an endless loop of magnetic tape, a system he had utilized for the periodising of analog signals. But now he stuck the tape on the surface of a drum, facing a writing- reading- and erasing head resp. and rotating at 100 rps. (Fig 2).


Thus the circulating `magnetophone' register was invented. Admittedly, these `dynamic' registers were much slower than the ultrasonic mercury delay lines used for the same purpose at the ACE. But all the troubles of synchronizing these with each others and with the peripherals, caused by changes of the mercury temperature, had been avoided!

In January 1948 Billing successfully tested a drum, capable of 192 20bit binary numbers plus the necessary circulating registers as well as the tracks synchronising the master clock. A first paper on a “Numeric Computer with a Magnetophone-Memory”, still using program control by punched tape, was presented at the 1948 conference of the GAMM (the german Society for Applied Mathematics and Mechanics). He could also demonstrate a bit-serially processing binary adder according Fig.1 to Prof.W. Heisenberg and others at the end of 1948.

But a realisation of a complete computer seemed to be a hopeless case at that time, as the effects of the currency reform in June 1948 cancelled all projects by a general lack of money. Thus a year later Billing followed an invitation to the University of Sydney in order to construct there a computer with a magnetic drum memory. However, he left a revised edition of his 1948/49 draft, now expanded to 34 pages, in Goettingen.

The Big Machine
But shortly after his arrival at Sydney Billing received a letter from W. Heisenberg, offering much better working conditions as before and, thanks to the upcoming (Marshall-Plan) ERP-funds, sufficient money became available for the hardware of a large computer, particularly needed by the Astrophysics Division of his institute, headed by L. Biermann. Thus Billing went back in June 1950 and revised the draft of 1949 to become the design of a Fully Automatic Computer (or Voll Automatische Rechenmaschine ‘VAR’). The proposed system featured a magnetic drum main memory for the storage of 2096 51-bit words allocating either a single fixed point number or two command-words. The use of app. 1200 vacuum tubes was estimated, the input/output should be performed with standard CCIR teletype equipment. That system became later the G2.
But the estimated time for the construction of that computer of at least 3 years was shocking for Biermann and his crew. They asked whether meanwhile a much smaller computer couldn't be built much faster. As the speed of desk computing is dominated by the time the operator needs for the entering of numbers, read from a form, into the computer and the subsequent writing of the results, read from the display, back to that form, a keyboard operated computer, featuring merely a few memory cells for the storing of parameters, constants and interim results would be sufficient. Yet the risk of errors due to the manual keying-in and writing-out of parameters and results could also be avoided. The speed of a single operation ought not to be much faster if compared with a mechanical desk computer..

The Small Machine
Based on the experiences gained from the experiments with the mechanical design of the small drum in 1948 and 1949 and the electronic circuitry working at a clock rate of app. 10 kHz, Billing during autumn 1950 designed the layout of a Semi Automatic Computer (or Halb Automatische Rechenmaschine “HAR”), the G1 Computer.

The G1 Drum
This paper showed the layout of the memory drum, including the 4 circulating registers. Dealing with the action of gates and delays it showed how left- and right-shifting of numbers will be performed, as well as the transmission of a number from one register to another. It also dealt with the arrangements for the decimal <> binary conversion during input and output. Moreover, in the app. 35 pages of the HAR paper the sets of waveforms controlling the gates for the execution of specific commands were analysed, including their timing. Figures 3,4,5 have been copied from that paper.


Fig.3 shows the memory drum of the G1 having a diameter of 8.8cm, a length of 17 cm and rotating at a speed of 50 rps. The leftmost track consisted of 144 mill-cut dents and generated the 7.2 kHz clock pulses in the associated pickup head wich, after amplification and shaping, were used for the synchronisation of the whole system. The other 13 tracks were magnetite-coated.

The first group of 4 tracks was used for the circulating registers, or ‘dynamic memories’. The distance between the writing- and the reading-heads, close to 180°, resulted in a double word length of 72 bits, taking into account the delay in the electronic circuitry. Due to the use of a ‘return-to-zero’ writing, an erasing head was needed between the reading- and writing-heads.
The other 9 tracks formed the ‘static memory’. Being subdivided into 4 sectors of 36 bits each, the ‘odd’ sectors of the next 5 tracks, corresponding to the high-word in the dynamic memories, are addressed as memory locations 0...9 resp. The even sectors of these 5 tracks were needed for the decimal to binary input conversion. The last 4 tracks provided the 16 static memory locations a0...a3; b0.,;,;,;...d3.
According to the selected address a set of 9 electromechanical relays connected the appropriate write/read-head to the output of the write/read-amplifier. In contrast to the dynamic memories now a modified Manchester phase encoding technique was used, thus allowing a simple overwriting.

G1 Block Diagram
Fig.4 shows a simplified block diagram of the G1: In addition to the 3 standard registers of an arithmetic unit a 4th. register, named ‘Distributor’(DIS), serves for the number flow between that unit, the memory drum and the number input/output to/from the user interface.
After I came to the group headed by H. Billing, this consisted of himself accompanied by H. ÷hlmann, a physicist for designing and building the G2 and myself for implementation of the G1 plans. The group was complemented by a designer for the mechanical parts, e.g. the magnetic drums, two mechanics in the workshop and a single electronics technician for the assembly and wiring of the chassis (after the year 1952 there were two of them). Because the group owned only a single oscilloscope my first task during learning about bits and bytes became the building of an oscilloscope for myself.

Implementation Step by Step
Guided by the HAR layout, the construction of the computer was performed stepwise: Because we didn’t have any electronic test equipment (besides of the two ‘scopes), the sequence of the implementation was governed by the demand, that already built parts of the machine have to serve as a sufficient test bed for the next device . At the G1 these steps were:
Production of the Drum for I synchronising the Master Clock Pulse Generator for II driving 2 Ring Counters of 14 stages each needed for III the selection of anyone of the 144 timing pulses to be used IV for the start/stop triggering of waveforms and V the generation of arbitrary bit patterns. The latter were necessary as VI test patterns for optimising of the read- and write amplifier circuits for the register- and the memory tracks of the magnetic drum.
During the final construction of these amplifiers with a pencil I sketched the circuitry of the Distributor Register (gates, amplifiers, shift registers, binary adder, invertors) on the back of large paper sheets (the fronts of which had been used for obsolete inventory lists). I used all in all 50 vacuum tubes. The technician had a hard job in deciphering my scribbles, but he did a fine job! After that chassis had been assembled, wired, mounted at the rack and connected to the amplifiers, pulse and power sources, it could be tested at first statically by switching the gates by applying constant voltages. During that tests the associated waveform generator chassis was assembled and wired. After mounting at the rack, wiring to the other devices and plugging of another 29 vacuum tubes, the Distributor could be tested dynamically.
As a last step of that phase, during springtime 1951, the typewriter (modified for electrical Input/Output by application of contacts and magnet coils on specific keys) was connected through a set of relays. Now the input and output from the typewriter to the memory, including decimal <> binary conversions and all memory activities could be practised.
Thus finally we had a test bed for the subsequent design and construction of the Arithmetic Unit which was again performed stepwise: At first the Accumulator(ACC) register, then the ACC waveform generator controlling addition and subtraction, had to be designed, constructed and tested. Subsequently the Multiplicand(MD) and Multiplier(MR) registers were built, sharing a single chassis, and then the associated waveform generators controlling multiplication and division. Being a latecomer, the square root function needed an own waveform generator, partially co-using waveforms of the MD/MR generator.

The Distributor
Fig.5 shows a more detailed diagram of the Distributor, called by Billing the ‘central part of this computer’:The output from the reading head R2, amplified and shaped by A2, is fed to a set of 3 gates where G0 proceeds the pulses without delay, G1 and G3 with delays of 1 and 3 bits resp. .to the inputs of the adder. In standard mode only G0 is open. This establishes a circulation period of exactly one double word. Otherwise, if G1 and G3 are opened, the circulating number will be multiplied by 10 at each turn. When a number is to be fetched, the gate GM connecting to the reading amplifier of the static memory is opened and the pulses are fed to the other input of the adder. If A2 is switched off and A1 switched on the circulation period becomes a single word length. According to the timing this copies the bits in the Distributor register from the low word positions into the high word positions or vice versa.
For the execution of a cyclic permutation of the 4 numbers, being stored in one of the tracks a...d, both amplifiers A1 and A2 as well as the erasing head E are switched off. Then all 4 sectors of the selected track are copied through GM onto the Distributor track. In the next step the writing head W is switched off and Amplifier A1 opened for writing back the Distributor track, delayed by one sector, to the static memory. Thus merely 2 revolutions of the drum are needed for the interchange of the 4 numbers.
In the even sectors preceding the memory locations 0....9, the binary equivalents of the numbers 0....9x10-10 are permanently stored. However, the value of these numbers is referring to the binary point in the subsequent high word. For a decimal input the low word according to the figure in the input is read through GM and added to the contents of the Distributor. In the next register cycle the content of the Distributor is multiplied by 10 as described above etc.
For the decimal output, the 4 bits to the left of the binary point are latched on a set of 4 Flipflops and transmitted to the I/O hardware before being cleared in the register. Thereafter the number is again multiplied by 10, thus bringing the next 4 bits into the leftmost position etc.
The net effect of all these actions is the ability of the G1 for decimal Input and Output without change of the contents of the registers of the arithmetic unit. An essential feature of a computer having a memory of merely 26 locations!

The Arithmetic Unit
The Arithmetic Unit consisted of the ACC, the MD- and the MR- registers. Each of theses dynamic memories had a circulating period of 72 bits, i.e. two words length. The bits 0 to 31 of a single word were used for the binary value of a number, bits 32+33 stored the sign and allowed for checking of overflows.
Negative numbers were represented by their absolute value and the sign, in order to simplify the I/O-conversion in the Distributor. Addition and subtraction into the ACC were performed by complementing the Augment/Diminuend and/or complementing the sum, depending on the signs of the operators and the operation to be performed.
As shifting of numbers is an inexpensive process in bit-serially operating registers, the number in MD could be shifted 1 bit to the right, that in MR to the left resp. Only in order to prevent overflowing of the number in the ACC, the contents could be halved by shifting the number 1bit to the right on command.
The multiplication had been performed top>down, i.e. according to the uppermost bit in MR, the contents of MD was sent to the ‘external’ input of the adder of the AC. Simultaneously, these numbers were shifted one bit accordingly. As the contents of the ACC were neither shifted nor cleared, all bits of a 32x32bit multiplication could be added into the Accumulator. Thus, during summing up of single operators or simple products, rounding problems couldn’t occur. And an expression like:
(a + b - cxd + exf) / g
could be input directly (without the brackets!). Only for storing in the memory or for the use of a result as a multiplicand, the two words were transferred from ACC to DIS and rounded to a single word before storing in the memory or in MD.
For speeding up purposes, a non-restoring division was implemented by adding a circuitry comparing the values in ACC at the output of the Adder/Inverter and the values in MD. In each step the contents of MD and MR were shifted in the same way as for multiplying. After 32 steps (or 16 revolutions of the drum) the last partial rest was cleared in the ACC, the quotient was copied from MR to ACC.
While these operations had been implemented and tested until the end of 1951, the idea came up to implement the square root extraction into the hardware because it would become the function needed at most. According to an algorithm by Zuse, published in 1951, the binary square-rooting can be regarded as a specific type of division. Presumably it is the algorithm Zuse had used for the implementation of that function into his Z3 and Z4 computers: The divisor is treated as a number, to be evolved from a single bit during the process. As the all functions for building the quotient in MR and copying of that number to ACC produced a ‘result’ root identical to the ‘calculating’ root, these functions could be used too.

The Command List
The available commands for the handling of operators are shown in the first two groups of the command list. Each of the commands 1...8 exists in two versions: The ‘a’ version is provided for the immediate execution by operation on numbers which had been input directly before into and converted by the Distributor. Else the ‘b’ version is executed: The command letter is stored until through the input of the next one or two characters the memory location is specified, from where the operand has to be fetched into the Distributor. Having loaded the Distributor with the operand, the stored command is executed.
Command 10 releases the transfer of the contents of the Accumulator to the Multiplicand - Register for the calculation of multi factorial products:
A term like : n x o x p x q may be coded as m0 x1 ] x2 ] x3
where 0,1.... denote the appropriate memory locations.
Command 13 is provided in order to overcome the disadvantages of a fixed addressing system, at least for the handling of iterating algorithms, e.g. for the stepwise numerical integration of differential equations. In the G1 the values of up to 4 operands may be stored in the groups a, b, c, d, e.g. for the actual and the 3 preceding steps of each operand. By the execution of the cyclic permutation commands, a similar effect is obtained at the end of an iterating step as by stepping up of an index in other systems.
During January 1952 all parts were assembled and all commands and operations tested successfully. Now the members of Biermanns astrophysics division could start digitally exercising at the G1. Digitally means here: By hitting the keys of the Input-Typewriter with their fingers.

The Punched Tape System
Already during autumn 1951 the idea came up, to connect a single punched tape reader in order to easify the implementation of often needed small programs e.g. for the calculation of trigonometric- or exponential functions. Discussions on that topic resulted at the turn of the years in the decision to implement 4 punched tape readers for general control purposes into the G1 System. The only readers available at that time were the 5-hole readers of the standard CCIR-TELEX systems operating at 7 characters/sec. They were rebuilt for parallel output on 5 signal lines. As all other parts of the G1 were ready and working, the output from the readers had to simulate an input from the contacts of the typewriter. This was done by a ‘pyramid’ of relays acting as a 5 to 32 binary decoder. The output contacts were connected in parallel to the appropriate input lines coming from the typewriter.
Additionally, the circuitry for the control of the readers had to be designed and build, as well as the circuitry for the control of a tape punch. The latter was to be used for punching all input typed into the typewriter (thus a program-tape could be punched in parallel to the execution of the input by the computer), for copying of tapes from reader to punch, and for punching of results in parallel to their printing.
Due to these works it became Easter 1952 before the tape system had been assembled. It worked correctly but unreliably: Not prior to that hard test by a continuous operation at 7 characters/sec, the unreliability of all our relays, bought as a bargain from wartime surplus shops, became noticeable. We have been saved by Zuse: He sent us app. 120 relays, his standard type used in his Z5 computer. While the new relay box was mechanically assembled I revised its circuitry, because the wiring of the old box was somewhat ‘haystacky’: New relays and wires had been added on demand for a new register or operation to be implemented. But after swapping the relay boxes at the end of May 1952 the G1 run perfectly well.

The Tape Commands
For running the tape system the last group of commands of Tab.1. had been added:
Sa (b,c,d) starts the appropriate tape reader. If this command is released from another reader, that ‘calling reader’ is stopped simultaneously. Command F stops the readers. By use of rotary switches on the operators panel an ‘embedded’ tape command may be released: When, after reading a number from any tape, the input terminating sign character (p or, n) is sensed, that tape is stopped and the selected tape reader is started.
The only conditional command which had been implemented into the G1 a year later, the tape Command ‘SI’ performs as follows:
IF that command is read from the tape ANDIF the contents of the ACC is not negative, THEN a ‘tape skip’ is performed: The reading is continued, the codes are sensed but no operation is performed.
ELSE standard execution is continued.
IF a tape skip is performed ANDIF the code for ‘I’ is sensed ANDIFNOT it had immediately preceded by a ‘S’, THEN the following commands will be executed again.
ELSE the mode of tape processing (executing/skipping) is not changed.
Thus a piece of calculation or merely the start of another tape reader may be skipped. A nested set of SI’s may as well be used, however the terminator for all skips is the same ‘I’!

The ‘Life’ of the G1
During the 1952 conference of the GAMM at Braunschweig, a paper on the G1 was presented on June, 6th by H. Billing, and the computer in full activity was presented to participants of that conference visiting Goettingen on the next day.

Years of regular Operation
In September 1952, the G1 was moved to the Max Planck Institut für Physik where it was running up to 24 hours a day and 7 days a week during the first years of operation. When it was permanently put off operation on June, 6th, 1958, this was after 5 years and 8 months or 49.560 hours. 33.946 hours during that time the G1 was switched on, a mean value of 16.5 h/d; 82% of that time could be used for computations, merely 5% were lost due to unexpected crashes (this includes the time for corrective maintenance), the rest was spent for preventive maintenance and other tests.
Considering these figures one should remember, that from 1952 until January 1955 the G1 had been the only electronic computer in Germany to be used for scientific computations. And when at the latter date the G2 went into full operation there were solely two computers for those applications, until the PERM at M¸nchen went into operation on May, 7th 1956! The magnetic drum is the only relic of the G1 and may now be seen at the ‘Deutsches Museum’ in München.

Learning by Doing
Because of the simplicity of the commands (Tab. 1) which could be learned in one hour, as well the proper use of the few memory cells and, if iterating procedures were envisaged, the use of the cyclic permutation, programming of the G1 could easily learned by doing. The scientists themselves could sit down at the typewriter, and, having the command list to the left, the algorithms to be programmed to the right, start practising the programming of the G1, And the computer answered immediately by typing the commands and the results. And that could be done without the aid of a programmer, there weren’t any! Nearly a decade had to pass before the same easiness of programming came back through the availability of BASIC or FOCAL responding immediately when running in interpreter mode.
Due to this many people from in-house and guests from elsewhere made their first acquaintance with programmable computers during dialogs with the G1. Some of these later on became directors of physical- or astrophysical institutes or heads of R&D computing centers in the industry. Thus the G1, in addition to the production of valuable results, assisted the introduction of computers in science and industry during the next half of the decade as well as the upcoming use of small computers in laboratories for the gathering and the pre-evaluation of experimental data.
A summary of the tasks which have been performed on the G1 (and the G2) until autumn 1955 is given in Tab.2.


The other Members of the Goettingen Computer Family
Table 3 shows all members of the G... Family and their main features. After the G1 and the G2 had been completed and were running in regular service, Billings team had already tested the application of new computer components. Apart from the long-life tubes and the crystal diodes,when the first ferrite cores arrived in spring 1952, they became most interesting. The use of the larger (9 mm dia.) cores in an improved version of magnetostatic delay lines was applied for a microprogrammed control system within the computer .


Fig. 6 shows the ‘head’ of a ‘micro-sequencer’ for several macro-operations: The operation-code of a macro command, split onto 2 predecoders magnetises one of the cores of a matrix decoder using the I/2 current adding method. Each of the matrix-cores acts as a ‘head-core’ to a single magnetostatic chain. At the first shift pulse, resetting all cores of the matrix, the next core of the associated line is set and the first micro-operation according to the macro-operation is released. With the next shift pulse the magnetic ‘1’ state is shifted to the next core in that chain and the subsequent micro operation is triggered. Conditional branching as well as looping could be performed within that system of magnetostatic shift registers.

The G1a
The design of the G1a aimed at a computer to be used alike the G1: Direct input of commands for immediate execution from a typewriter and output of results to that device. Floating point arithmetic was used in order to abandon the problems of keeping numbers within a fixed range. The magnetic drum stored 1800 words on 30 tracks having 60 words of 60 bits each. Due to this memory size, a separate Distributor register for decimal I/O could be omitted. The communication between ACC and memory was handled by the MD-Register including the cyclical permutation. There were 10 track switching relays connected to the rotor arms of 10 selectors, each of these connecting in turn to one of the 30 tracks. Through programmed positioning of the selectors an address interpretation alike to bank switching was performed. Program control was performed by a set of 10 mechano-optical tape readers of own design at a speed of up to 180 chars/sec. The complex set of waveform generators as in the G1 could be simplified by using magnetostatic delay lines as ring counters and for microprogramming of the trigger-pulses switching the gates in the registers etc. 2 G1a’s were built at Goettingen. One came into operation there at the Max Planck Institute for Hydrodynamics, the other came to the Institute for Plasmaphysics at Juelich in 1958 and was moved 1961 to a high school at Neuss from where it was recovered later and finally moved to the Deutsches Museum at Muenchen.

The G3
As a successor of the G3 and using the new technologies H. Billing planned the G3. A first step in that direction was the construction of a 16x10 matrix using 2.7 mm ferrite cores. After September 1952 that matrix could be used for testing other cores, addressing methods and other features. The G3 became one of the ‘big’ machines (in the terms of these years). It was the first computer owning a hardware stack pointer and stack registers. As compared with other contemporary parallel computers having a word length of app. 40 bits, the amount of 1500 tubes plugged into the G3 is relatively small. This is caused by the extensive use of magnetostatic delay lines for microprogramming of all operations. App. 600 cores were used in that lines. Because the ferrite core chains had been plug-in modules, a change of existing complex operations could easily be done as well as the adding of new functions. Thus a digital tape recorder and a graphic display were attached to the G3 in the last years of operation. A single plane of the core storage can be seen in the exhibition in this house. May be the only relic of that last member of the Goettingen Computer Family.

Table 1

Table of Commands for the Tape controlled Computer G1

This table shows the contents of the Registers A (Accumulator), M (Multiplicand R.) and z (Memory location), expressed by contents before the operation as <>; - = no change; 0 = cleared. Memory locations are 0,.......,9 and the ‘cyclic’ groups a0,...,a3; b0,...,b3; c0,...,c3; d0,...,d3. Z signifies a decimal number of max. 10 figures to be entered from the keyboard or the punched tape, beginning with the first figure (<7) to the left of the decimal point and ending with the sign (p or n).


Operations with entered numbers Operations with stored numbers

No. Operation A M z No. Operation A M z
1a Z+ <A> + Z - - 1b + z <A> + <z> - -
2a Z - <A> - Z - - 2b - z <A> - <z> - -
3a° Z m - Z - 3b° m z - <z> -
4a Z ´ <A> + Z´<M> 0 - 4a ´ z <A> + <z>´<M> 0 -
5a Z ´ <A> - Z´<M> 0 - 5b ´ z <A> - <z>´<M> 0 -
6a Z : <A> : Z 0 - 6b : z <A> : <z> 0 -
7a Z ® z - - Z 7b ® z 0 - <A>
8a Z D
Print the number Z
- - - 8b D z
Print the number <z>
- - -
8a Z L
Print + punch the number Z
- - - 8b L z
Print + punch the number <z>
- - -
      Other operations          
10° ] 0 <A>   13 a Cyclical permutation
b, c, d, accordingly
  <a0> ® a1
® a2
® a3
® a0
11 Ö Ö<A> 0 -        
12 h <A> : 2 - -        
      Tape Operations          
14 Sa Start tape reader a (b,c,d accordingly)     15 F Stop tape reader    
16 SI IF <A> >0 then continue tape reading, but don’t execute the commands until >>>>>>>>>     17 I Execute tape input again    


° Must be followed by operation 4 or 5 !




Table 3 : The Goettinger Computer Family


Computer G1 G2 G1a G3
Operation Mode Serially, 2 ops/sec Serially, 30 ops/sec Serially, 20 flops/sec Parallel 5000 flops/sec
Memory 26 words of 32 bits 2048 words of 50+1 bits 1840 words of 60 bits 4096 words of 42+1 bits
  Magnetic Drum Magnetic Drum Mag. Drum Ferrite Core Matrix
  Paper Tape      
Number fixed point fixed point floating point floating point
representation z < 8 z < 8 43 bit mant. 33 bit mant.
      8 bit exp. 9 bit exp.
      1 bit marker 1 bit marker
Program Control punched tape memory punched tape memory
  4 readers (2 cmds./word) 10 readers 180 ch/sec (2 cmds/word)
  typewriter   typewriter  
Commands 16 32 22 64
Micro - Coding     magnetostatic magnetostatic
      delay lines delay lines
Address - no, but yes, 1 index - no, but yes, 7 index -
Modification cyclic permutation register cyclic permutation registers, bracket -
  4 x 4 conditional 30 x 2...60 words handling, 16 word
    branching 30 x 10 bank switching hardware stack
Lifetime 1.11.52 - 30.6.58 1.1.55 - 30.6.61 a)1958 - 1963) 1.1.61 - 9.11.72
  =49.560 hrs. =56.952 hrs. b)1960 - 1970 =104.200 hrs.
Operating time 33.946 hrs 36.076 c)1958 -.1961/68 (88) 57.300 hrs.
equivalent to =16.5 hrs./day =15.2 hrs./day no specific statistics =13.2 hrs./day
Efficiency 82% 78% app. 80 % 85.9%
Hardware crashes 5% 5% and corr. maintenance 1.1 %

a)AVA Goettingen  b)Math.I. Helsinki c)IPP Juelich - Neuss -(Dt. Museum Muenchen )